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MC10EP131, MC100EP131 3.3V / 5V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock
The MC10/100EP131 is a Quad Master-slaved D flip-flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables. With AC performance faster than the E131 device, the EP131 is ideal for applications requiring the fastest AC performance available. Each flip-flop may be clocked separately by holding Common Clock (CC) LOW and CC HIGH, then using the differential Clock Enable inputs for clocking (C0-3, C0-3). Common clocking is achieved by holding the differential inputs C0-3 LOW and C0-3 HIGH while using the differential Common Clock (CC) to clock all four flip-flops. When left floating open, any differential input will disable operation due to input pulldown resistors forcing an output default state. Individual asynchronous resets (R0-3) and an asynchronous set (SET) are provided. Data enters the master when both CC and C0-3 are LOW, and transfers to the slave when either CC or C0-3 (or both) go HIGH. The 100 Series contains temperature compensation.
http://onsemi.com MARKING DIAGRAM*
LQFP-32 FA SUFFIX CASE 873A 32
MCXXX EP131 AWLYYWW
1 XXX = 10 or 100 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week *For additional information, see Application Note AND8002/D
* * * * * * *
460 ps Typical Propagation Delay Maximum Frequency > 3 GHz Typical Differential Individual and Common Clocks Individual Asynchronous Resets Asynchronous Set PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V Open Input Default State
ORDERING INFORMATION
Device MC10EP131FA MC10EP131FAR2 MC100EP131FA Package LQFP-32 Shipping 250 Units/Tray
LQFP-32 2000 Tape & Reel LQFP-32 250 Units/Tray
* * Safety Clamp on Inputs * Q Output Will Default LOW with Inputs Open or at VEE
MC100EP131FAR2 LQFP-32 2000 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2004
1
January, 2004 - Rev. 7
Publication Order Number: MC10EP131/D
MC10EP131, MC100EP131
Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 S D3 24 VCC C3 C3 VEE D3 R3 SET D2 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 23 22 21 20 19 18 17 16 15 14 13 VCC R0 D0 VCC C0 C0 R1 VEE D2 C2 C2 R2 SET CC R2 C2 C2 CC CC C1 C1 D1 CC Q R Q2 S D Q Q2 C3 C3 R3 Q R Q3 D Q Q3
32-Lead LQFP Pinout (Top View)
12 11 10 9
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
R1 C1 C1 R Q Q1
Figure 1. 32-Lead LQFP Pinout (Top View)
PIN DESCRIPTION
PIN D0-3* C0-3*, C0-3* CC*, CC* R0-3* SET* Q0-3, Q0-3 VCC VEE FUNCTION ECL Data Inputs ECL Separate Clock Inputs ECL Common Clock Inputs ECL Asynchronous Reset ECL Asynchronous Set ECL Data Outputs Positive Supply Negative Supply
D1
D
Q S
Q1
R0 C0 C0 D0 D Q S Q0 R Q Q0
VEE
* Pins will default LOW when left open.
Figure 2. Logic Diagram
TRUTH TABLE
D L H X X X S* L L H L H R* L L L H H CLK Z Z X X X Q L H H L Undef
Z = LOW to HIGH Transition * Pins will default low when left open.
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MC10EP131, MC100EP131
ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 kW N/A > 2 kV > 100 V > 2 kV Level 2 Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in 935 Devices
Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Symbol VCC VEE VI Iout IBB TA Tstg JA JC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode In ut Voltage Input NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder 0 LFPM 500 LFPM std bd > 2 to 3 sec @ 248C 32 LQFP 32 LQFP 32 LQFP Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 6 -6 6 -6 50 100 0.5 -40 to +85 -65 to +150 80 55 12 to 17 265 Units V V V V mA mA mA C C C/W C/W C/W C
2. Maximum Ratings are those values beyond which device damage may occur.
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MC10EP131, MC100EP131
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 5) Input HIGH Current Input LOW Current 0.5 Min 70 2165 1365 2090 1365 2.0 Typ 95 2290 1490 Max 120 2415 1615 2415 1690 3.3 150 0.5 Min 70 2230 1430 2155 1460 2.0 25C Typ 95 2355 1555 Max 120 2480 1680 2480 1755 3.3 150 0.5 Min 70 2290 1490 2215 1490 2.0 85C Typ 95 2415 1615 Max 120 2540 1740 2540 1815 3.3 150 Unit mA mV mV mV mV V A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 4. All loading with 50 to VCC-2.0 volts. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 7) Output LOW Voltage (Note 7) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 8) Input HIGH Current Input LOW Current 0.5 Min 70 3865 3065 3790 3065 2.0 Typ 95 3990 3190 Max 120 4115 3315 4115 3390 5.0 150 0.5 Min 70 3930 3130 3855 3130 2.0 25C Typ 95 4055 3255 Max 120 4180 3380 4180 3455 5.0 150 0.5 Min 70 3990 3190 3915 3190 2.0 85C Typ 95 4115 3315 Max 120 4240 3440 4240 3515 5.0 150 Unit mA mV mV mV mV V A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 7. All loading with 50 to VCC-2.0 volts. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 9) -40C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 10) Output LOW Voltage (Note 10) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 11) Input HIGH Current Input LOW Current 0.5 Min 70 -1135 -1935 -1210 -1935 VEE+2.0 Typ 95 -1010 -1810 Max 120 -885 -1685 -885 -1610 0.0 150 0.5 Min 70 -1070 -1870 -1145 -1870 VEE+2.0 25C Typ 95 -945 -1745 Max 120 -820 -1620 -820 -1545 0.0 150 0.5 Min 70 -1010 -1810 -1085 -1810 VEE+2.0 85C Typ 95 -885 -1685 Max 120 -760 -1560 -760 -1485 0.0 150 Unit mA mV mV mV mV V A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. Input and output parameters vary 1:1 with VCC. 10. All loading with 50 to VCC-2.0 volts. 11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP131, MC100EP131
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 13) Output LOW Voltage (Note 13) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 14) Input HIGH Current Input LOW Current 0.5 Min 70 2155 1355 2075 1355 2.0 Typ 95 2280 1480 Max 120 2405 1605 2420 1675 3.3 150 0.5 Min 75 2155 1355 2075 1355 2.0 25C Typ 97 2280 1480 Max 120 2405 1605 2420 1675 3.3 150 0.5 Min 80 2155 1355 2075 1355 2.0 85C Typ 105 2280 1480 Max 130 2405 1605 2420 1675 3.3 150 Unit mA mV mV mV mV V A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 13. All loading with 50 to VCC-2.0 volts. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 16) Output LOW Voltage (Note 16) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 17) Input HIGH Current Input LOW Current 0.5 Min 70 3855 3055 3775 3055 2.0 Typ 95 3980 3180 Max 120 4105 3305 4120 3375 5.0 150 0.5 Min 75 3855 3055 3775 3055 2.0 25C Typ 97 3980 3180 Max 120 4105 3305 4120 3375 5.0 150 0.5 Min 80 3855 3055 3775 3055 2.0 85C Typ 105 3980 3180 Max 130 4105 3305 4120 3375 5.0 150 Unit mA mV mV mV mV V A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 16. All loading with 50 to VCC-2.0 volts. 17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 18) -40C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 19) Output LOW Voltage (Note 19) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 20) Input HIGH Current Input LOW Current 0.5 Min 70 -1145 -1945 -1225 -1945 VEE+2.0 Typ 95 -1020 -1820 Max 120 -895 -1695 -880 -1625 0.0 150 0.5 Min 75 -1145 -1945 -1225 -1945 VEE+2.0 25C Typ 97 -1020 -1820 Max 120 -895 -1695 -880 -1625 0.0 150 0.5 Min 80 -1145 -1945 -1225 -1945 VEE+2.0 85C Typ 105 -1020 -1820 Max 130 -895 -1695 -880 -1625 0.0 150 Unit mA mV mV mV mV V A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 18. Input and output parameters vary 1:1 with VCC. 19. All loading with 50 to VCC-2.0 volts. 20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP131, MC100EP131
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21)
-40C Symbol fmax Characteristic Maximum Frequency (See Figure 3. Frequency vs. VOUTpp and JITTER) Propagation Delay to Output Differential C0-3 CC R0-3 SET 320 320 320 300 290 120 SET, R0-3 550 Min Typ >3 Max Min 25C Typ >3 Max Min 85C Typ >3 Max Unit GHz
tPLH, tPHL
450 450 430 430 210 80 400 0.2
520 520 520 550
380 400 380 380 290 120 550
460 500 480 460 210 80 400 0.2
580 600 580 580
450 450 450 400 350 120 550
560 560 560 530 280 80 400 0.2
650 650 700 650
ps
tRR tS tH tPW tJITTER
Set/R0-3 Recovery Setup Time Hold Time Minimum Pulse Rate
ps ps
Cycle-to-Cycle Jitter (See Figure 3. Frequency vs. VOUTpp and JITTER) Output Rise/Fall Times (20% - 80%) Q, Q 110
<1
<1
<1
ps
tr tf
180
250
125
200
275
150
230
300
ps
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V.
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MC10EP131, MC100EP131
800 700 VOUTpp (mV) 600 500 400 300 200 8 7 6 5 4 3 2 1 JITTEROUT ps (RMS)
Figure 4. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 - Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404 AN1405 AN1406 AN1504 AN1568 AN1650 AN1672 AND8001 AND8002 AND8009 AND8020 - - - - - - - - - - - ECLinPS Circuit Performance at Non-Standard VIH Levels ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) Metastability and the ECLinPS Family Interfacing Between LVDS and ECL Using Wire-OR Ties in ECLinPS Designs The ECL Translator Guide Odd Number Counters Design Marking and Date Codes ECLinPS Plus Spice I/O Model Kit Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
EEEEEEE EEEEEEE
0 0 1000 2000 Q Driver Device Q
100
(JITTER) 3000 4000 5000 6000
FREQUENCY (MHz)
Figure 3. Frequency vs. VOUTpp and JITTER
D Receiver Device D 50 50
VTT VTT = VCC - 2.0 V
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EE EE
MC10EP131, MC100EP131
PACKAGE DIMENSIONS
LQFP FA SUFFIX 32-LEAD PLASTIC PACKAGE CASE 873A-02 ISSUE A
A
32 4X 25
A1
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V P DETAIL Y
17
AE
V1 AE DETAIL Y
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
N
F
8X
D
M_ R
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
J
CE
SECTION AE-AE
X DETAIL AD
GAUGE PLANE
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0.250 (0.010)
H
W
K
Q_
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
-T-, -U-, -Z-
EE EE EE
MC10EP131, MC100EP131
Notes
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MC10EP131, MC100EP131
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MC10EP131/D

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